Array substrate for liquid crystal display device and method of manufacturing the same

ABSTRACT

An array substrate for a liquid crystal display device includes a substrate; a semiconductor layer on the substrate; a gate electrode on the semiconductor layer; source and drain electrodes on and in contact with the semiconductor layer; and an oxide layer on the gate electrode, the oxide layer including a plurality of metal atoms, wherein each of the source and drain electrodes includes a pattern of metal substantially made of the plurality of metal atoms.

This application claims the benefit of Korean Patent Application No.10-2013-0131396, filed on Oct. 31, 2013, which is hereby incorporated byreference for all purposes as if fully set forth herein.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present disclosure relates to an array substrate for a liquidcrystal display device (LCD), and more particularly, to an arraysubstrate for an LCD including a coplanar type thin film transistor(TFT) and a method of manufacturing the same.

2. Discussion of the Related Art

With the advancement of information society, demand for display devicein various forms has increased. Recently, various flat panel displaydevices, such as a liquid crystal display device (LCD), a plasma displaypanel (PDP), and an organic light emitting diode display (OLED), havebeen used.

Among these flat panel display devices, the LCD has advantages of lowpower consumption due to low driving voltage and portability, and thusis widely used in various fields, such as laptop computer, monitor,spacecraft, and airplane.

Particularly, an active matrix LCD device, in which a thin filmtransistor (TFT) as a switching element is formed in each of pixelsarranged in a matrix, has been commonly used.

The TFT are categorized into various types according to positions of agate electrode, for example, a staggered type, an inverted staggeredtype, and a coplanar type.

The coplanar type TFT has excellent element property because an activelayer thereof is not damaged when etching source and drain electrodes.

The coplanar type TFT has a structure that a gate electrode, and thesource and drain electrodes are located over the active layer.

FIG. 1 is a cross-sectional view illustrating the coplanar type TFTaccording to the related art.

Referring to FIG. 1, a buffer layer 11 is formed on a substrate 10. Anactive layer 24 is formed on the buffer layer 11 and includes a channelregion 24 a and source and drain regions 24 b and 24 c at both sides,and a first insulating layer 15 a is formed on the active layer 24.

A gate electrode 21 is formed on the first insulating layer 15 a, and asecond insulating layer 15 b is formed on the gate electrode 21 andincludes contact holes exposing the source and drain regions 24 b and 24c. Source and drain electrodes 22 and 23 are formed on the secondinsulating layer 15 b and contact the source and drain regions 24 b and24 c, respectively.

The active layer 24, the gate electrode 21, and the source and drainelectrodes 22 and 23 as described above form a coplanar type TFT.

A third insulating layer 15 c is formed on the source and drainelectrodes 22 and 23 and includes a contact hole exposing the drainelectrode 23. A pixel electrode 18 is formed on the third insulatinglayer 15 c and contacts the drain electrode 23.

The active layer 24 is made of a ZnO based semiconductor material, thushas a high mobility and meets a constant current test condition, andthus is applicable to a large-sized display.

ZnO is a material that can have a conductor property, a semiconductorproperty, or a nonconductor property according to a content of oxygen.Accordingly, the active layer using ZnO is applicable to a large-sizeddisplay, for example, LCD or OLED.

However, the second insulating layer 15 b is formed to prevent theactive layer 24 of the ZnO based material from being exposed, and thus anumber of mask processes increases.

Thus, steps of production processes increase, thus production costincreases, and productivity decreases.

SUMMARY OF THE INVENTION

Accordingly, the present invention is directed to an array substrate fora liquid crystal display device (LCD) and method of manufacturing thesame that substantially obviates one or more of the problems due tolimitations and disadvantages of the related art.

An advantage of the present invention is to provide an array substratefor a liquid crystal display device (LCD) and method of manufacturingthe same that can decrease steps of production processes and improveproductivity.

Additional features and advantages of the invention will be set forth inthe description which follows, and in part will be apparent from thedescription, or may be learned by practice of the invention. These andother advantages of the invention will be realized and attained by thestructure particularly pointed out in the written description and claimshereof as well as the appended drawings.

To achieve these and other advantages and in accordance with the purposeof the present invention, as embodied and broadly described herein, anarray substrate for a liquid crystal display device may include asubstrate; a semiconductor layer on the substrate; a gate electrode onthe semiconductor layer; source and drain electrodes on and in contactwith the semiconductor layer; and an oxide layer on the gate electrode,the oxide layer including a plurality of metal atoms, wherein each ofthe source and drain electrodes includes a pattern of metalsubstantially made of the plurality of metal atoms.

In another aspect, a method of an array substrate for a liquid crystaldisplay device may include forming semiconductor layer on a substrate;forming a gate electrode on the semiconductor layer; forming a firstmetal layer and a second metal layer sequentially on the gate electrode;patterning the first metal layer and the second metal layer to form afirst metal pattern and a second metal pattern, respectively; etchingthe second metal pattern to expose a portion of the first metal patternand form a first source pattern and a first drain pattern; and oxidizingthe exposed portion of the first metal pattern to form an oxide layer, asecond source pattern and a second drain pattern, wherein the first andsecond source patterns form a source electrode, and the first and seconddrain patterns form a drain electrode.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are included to provide a furtherunderstanding of the invention and are incorporated in and constitute apart of this specification, illustrate embodiments of the invention andtogether with the description serve to explain the principles of theinvention. In the drawings:

FIG. 1 is a cross-sectional view illustrating the coplanar type TFTaccording to the related art;

FIG. 2 is a cross-sectional view illustrating an array substrate for anLCD according to an embodiment of the present invention; and

FIGS. 3A to 3H are cross-sectional views illustrating a method formanufacturing an array substrate of an LCD according to an embodiment ofthe present invention.

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS

Reference will now be made in detail to exemplary embodiments, examplesof which are illustrated in the accompanying drawings. The samereference numbers may be used throughout the drawings to refer to thesame or like parts.

A thin film transistor (TFT) of the present invention may be apolycrystalline type TFT, an amorphous type TFT, or oxide type TFT. Forthe purpose of explanations, the oxide TFT is described in theembodiment below by way of example.

FIG. 2 is a cross-sectional view illustrating an array substrate for aliquid crystal display device (LCD) according to an embodiment of thepresent invention.

Referring to FIG. 2, in the array substrate for the LCD, a buffer layer111 is formed on a substrate 110. Alternatively, the buffer layer 111may be eliminated.

An active layer 124 as a semiconductor layer is formed on the bufferlayer 111 and includes a channel region 124 a and source and drainregions 124 b and 124 c at both sides, and a first insulating layer 115a is formed on the channel region 124 a and covers a part of the channelregion 124 a.

A gate electrode 121 is formed on the first insulating layer 115 a. Anoxide layer 126 covers the gate electrode 121, substantiallycorresponding to the channel region 124 a.

Second source and drain patterns 122 b and 123 b cover and contact thesource and drain regions 124 b and 124 c, respectively. First source anddrain patterns 122 a and 123 a are formed on and substantially have thesame pattern as the second source and drain patterns 122 b and 123 b,respectively. The first and second source patterns 122 a and 122 b forma source electrode 122, and the first and second drain patterns 123 aand 123 b form a drain electrode 123.

The active layer 124, the gate electrode 121, and the source and drainelectrodes 122 and 123 as described above form a coplanar type TFT.

A second insulating layer 115 b is formed entirely on the secondsubstrate 110 having the source and drain electrodes 122 and 123, andincludes a contact hole exposing a part of the drain electrode 123. Apixel electrode 118 is formed on the second insulating layer 115 b andcontacts the drain electrode 123 via the contact hole of the secondinsulating layer 115 b.

The active layer 124 is formed of a ZnO based semiconductor material,for example, IGZO. ZnO is a material that can have a conductor property,a semiconductor property, or a nonconductor property according to acontent of oxygen. Accordingly, the active layer 124 using ZnO isapplicable to a large-sized display, for example, LCD or OLED.

In the embodiment, by adjusting a concentration of oxygen in a reactiongas during the sputtering process, a concentration of carrier in theactive layer 124 can be adjusted, and thus properties of the TFT can beadjusted.

Since the active layer 124 is made of the ZnO based semiconductormaterial, it has a high mobility and meets a constant current testcondition, and thus is applicable to a large-sized display.

The active layer 124 is covered by the source and drain electrodes 122and 123 and the oxide layer 126.

The oxide layer 126 is formed by oxidizing a material that is used toform the second source and drain patterns 122 b and 123 b and is locatedat a region corresponding to the channel region 124 a. Accordingly, theoxide layer 126 covers the channel region 124 a, and the source anddrain electrodes 122 and 123 cover the source and drain regions 124 band 124 c, respectively. Accordingly, the second insulating layer (15 bof FIG. 1) of the related art is eliminated. Thus, a number of maskprocesses can be reduced, and production cost can be reduced andproductivity can be improved.

The oxide layer 126 contacts the second source and drain patterns 122 band 123 b at both sides.

The oxide layer 126 may extend such that it covers a part of the sourceand drain regions 124 b and 124 c.

FIGS. 3A to 3H are cross-sectional views illustrating a method formanufacturing an array substrate of an LCD according to an embodiment ofthe present invention.

Referring to FIG. 3A, the ZnO based semiconductor material is depositedon the buffer layer 111 to form the active layer 124, and then the firstinsulating layer 115 a and the gate electrode 121 are sequentiallyformed on the active layer 124.

In more detail, the ZnO bsed semicondutor material is patterned in afirst mask process to form the active layer 124.

The ZnO bsed semicodncutor material may be formed , for example, using acomplex target of Ga₂O₃, In₂O₃ and ZnO in a sputtering method, andalternatively, in a CVD (chemical vapor deposition) method, or ALD(atomic layer deposition) method.

The first insulating layer 115 a may be formed of an inorganicinsulating material, for example, SiNx or SiO₂, or a high dielectricconstant oxide material, for example, hafnium oxide or aluminum oxide.

The first insulating material 115 a may be formed in a CVD method, orPECVD (plasma enhanced CVD) method.

The gate electrode 121 may be formed of a conductive material having alow resistance and being opaque, for example, Al, Al alloy, W, Cu, Ni,Cr, Mo, Ti, Pt or Ta, or a transparent conductive material, for example,ITO or IZO. Alternatively, the gate electrode 121 may have amultiple-layered structure using at least two of the above materials.

The first gate insulating material and the gate electrode material aredeposited entirely on the substrate 110 and patterned in a second maskprocess to form the first insulating layer 115 a and the gate electrode121.

The first insulating layer 115 a and the gate electrode 121 may beformed using a dry etching process.

Then, referring to FIG. 3B, a first metal layer 113 and a second metallayer 114 are sequentially formed on the substrate 110 having the gateelectrode 121.

The first metal layer 113 may be formed of a metal having a low contactresistance for a conductor to meet a high mobility and a constantcurrent test condition, for example, Al, Al alloy, Cu, Ni, Cr, Ti, Pt,Ta, Ti alloy, Mo or Mo alloy. For example, the first metal layer 113 mayhave a contact resistance less than the second metal layer 114 inconnection with the source and drain regions 124 b and 124 c.

Because the second metal layer 114 may not be in direct contact with thesource and drain regions 124 b and 124 c, a contact resistance of thesecond metal layer 114 may not be considered. Accordingly, the secondmetal layer 114 may be formed of a metal having a specific resistanceless than the first metal layer 113, for example, Cu, Au or Mo.

The first metal layer 113 may have a thickness of about 200 angstroms orless to meet a high mobility and a constant current test condition, andpreferably has about 100 angstroms to about 200 angstroms.

A photoresist layer 128 is formed entirely on the substrate 110 havingthe first and second metal layers 113 and 114.

Then, referring to FIG. 3C, in a third mask process, exposing thephotoresist layer 128 selectively to light is conducted.

The light exposure may be conducted using a single photo mask or ahalftone mask 130. In the embodiment, the halftone mask 130 ispreferably used to reduce a number of mask processes.

The halftone mask 130 includes a transmissive portion I transmitting, asemi-transmissive portion II, and a blocking portion III.

Referring to FIG. 3D, after the light exposure using the halftone mask130, a developing process of the photoresist layer 128 is conducted.Accordingly, a portion of the photoresist layer 128 corresponding to thetransmissive portion I is removed, a portion of the photoresist layer128 corresponding to the semi-transmissive portion II is partiallyremoved to become a first photoresist pattern 128 a, and a portion ofthe photoresist layer 128 corresponding to the blocking portion IIIremains and becomes a second photoresist pattern 128 b that is thickerthan the first photoresist pattern 128 a. The second photoresist pattern128 b is located at each of both sides of the first photoresist pattern128 a. In other words, the second photo resist patterns 128 b arelocated corresponding to the source and drain regions 124 b and 124 c.

The first and second metal layers 113 and 114 are patterned using thefirst and second photoresist patterns 128 a and 128 b.

In other words, referring to FIG. 3E, the first and second metal layers113 and 114 are etched using the first and second photoresist patterns128 a and 128 b to form the first and second metal patterns 113 a and114 a. This etching process may be a wet etching process. The first andsecond metal patterns 113 a and 114 a are formed continuously over theactive layer 124.

Then, an ashing process is conducted to remove the first photoresistpattern 128 a and partially remove the second photoresist patterns 128 bby a thickness of the first photoresist pattern 128 a. The ashed secondphotoresist patterns 128 b corresponding to the source and drain regions124 b and 124 c become third and fourth photoresist patterns 128 c and128 d.

Then, referring to FIG. 3F, the second metal pattern 114 a is etchedusing the third and fourth photoresist patterns 128 c and 128 d. Thisetching process may be a dry etching process. Accordingly, the firstsource and drain patterns 122 a and 123 a spaced apart from each otherare formed.

Then, a portion of the first metal pattern 113 a exposed between thethird and fourth photoresist patterns 128 c and 128 d is oxidized. Forexample, an oxygen plasma treatment or a thermal treatment under oxygenatmosphere for a predetermined time is conducted to oxidize the exposedportion of the first metal pattern 113 a. Accordingly, the exposedportion of the first metal pattern 113 a becomes the oxide layer 126.

The oxide layer 126 may be made of at least one of AlxOx, AlxOx alloy,CuxOx, NixOx, CrxOx, TixOx, PtxOx, TaxOx, TixOx alloy, MoxOx and MoxOxalloy.

The oxide layer 126 is a nonconductor and functions as an insulator.Accordingly, the first metal pattern 113 a is modified into the secondsource and drain patterns 122 b and 123 b and the oxide layer 126between the second source and drain patterns 122 b and 123 b.

After forming the oxide layer 126, the third and fourth photoresistpatterns 128 c and 128 d are stripped using an ashing process.

Accordingly, the source electrode 122 including the first and secondsource patterns 122 a and 122 b, and the drain electrode 123 includingthe first and second drain patterns 123 a and 123 b are formed.

Then, referring to FIG. 3G, the second insulating layer 115 b is formedentirely on the substrate 110 having the source and drain electrodes 122and 123. Then, the second insulating layer 115 b is patterned in afourth mask process to form a contact hole exposing a part of the drainelectrode 123.

Then, referring to FIG. 3H, a third conductive layer is formed entirelyon the second insulating layer 115 b and is patterned in a fifth maskprocess to form a pixel electrode 118 contacting the drain electrode 123through the contact hole of the second insulating layer 115 b.

Through the above-described processes, an array substrate of an LCDaccording to an embodiment is manufactured.

In the array substrate, the active layer 124 is made of the ZnO basedmaterial, and thus the TFT has a high mobility and meets a constantcurrent test condition. The LCD is applicable to a large-sized display.

Further, during the manufacturing process, the first metal pattern 113 ais used to form the source and drain electrodes 122 and 123 and coverthe active layer 124, and a portion of the first metal pattern 113 acorresponding to the channel region 124 a is oxidized and covers thechannel region 124 a. Accordingly, the second insulating layer (15 b ofFIG. 1) according to the related art is eliminated, and thus a number ofmask processes can be reduced, thereby reducing production cost andimproving productivity.

It will be apparent to those skilled in the art that variousmodifications and variation can be made in the present invention withoutdeparting from the spirit or scope of the invention. Thus, it isintended that the present invention cover the modifications andvariations of this invention provided they come within the scope of theappended claims and their equivalents.

What is claimed is:
 1. An array substrate for a liquid crystal displaydevice, comprising: a substrate; a semiconductor layer on the substrate;a gate electrode on the semiconductor layer; source and drain electrodeson and in contact with the semiconductor layer; and an oxide layer onthe gate electrode, the oxide layer including a plurality of metalatoms, wherein each of the source and drain electrodes includes apattern of metal substantially made of the plurality of metal atoms. 2.The array substrate of claim 1, wherein the source electrode includes afirst source pattern and a second source pattern below the first sourcepattern, and the drain electrode includes a first drain pattern and asecond drain pattern below the first drain pattern, and wherein theoxide layer is located at the same layer as the second source and drainpatterns.
 3. The array substrate of claim 2, wherein the first sourceand drain patterns has a specific resistance less than the second sourceand drain patterns, and has a contact resistance for a conductor greaterthan the second source and drain patterns.
 4. The array substrate ofclaim 2, wherein the first source and drain patterns are made of one ofCu, Au and Mo, and the second source and drain patterns are made of oneof Al, Al alloy, Cu, Ni, Cr, Ti, Pt, Ta, Ti alloy, Mo and Mo alloy. 5.The array substrate of claim 1, wherein the oxide layer is made of oneof AlxOx, AlxOx alloy, CuxOx, NixOx, CrxOx, TixOx, PtxOx, TaxOx, TixOxalloy, MoxOx and MoxOx alloy.
 6. The array substrate of claim 1, whereinthe semiconductor layer includes a channel region and source and drainregions at both sides, and wherein a first insulating layer is on thechannel region.
 7. The array substrate of claim 6, wherein the gateelectrode is on the first insulating layer.
 8. The array substrate ofclaim 1, further comprising: a second insulating layer that is on thesource and drain electrodes and includes a contact hole exposing thedrain electrode; and a pixel electrode that is on the second insulatinglayer and contacts the drain electrode through the contact hole.
 9. Amethod of an array substrate for a liquid crystal display device,comprising: forming semiconductor layer on a substrate; forming a gateelectrode on the semiconductor layer; forming a first metal layer and asecond metal layer sequentially on the gate electrode; patterning thefirst metal layer and the second metal layer to form a first metalpattern and a second metal pattern, respectively; etching the secondmetal pattern to expose a portion of the first metal pattern and form afirst source pattern and a first drain pattern; and oxidizing theexposed portion of the first metal pattern to form an oxide layer, asecond source pattern and a second drain pattern, wherein the first andsecond source patterns form a source electrode, and the first and seconddrain patterns form a drain electrode.
 10. The method of claim 9,wherein forming the first and second metal patterns includes: formingfirst and second photoresist patterns on the second metal layer; andpatterning the first and second metal layers using the first and secondphotoresist patterns to form the first and second metal patterns. 11.The method of claim 10, wherein the first and second photoresistpatterns are formed using a halftone mask.
 12. The method of claim 10,wherein forming the second source and drain patterns includes: removingthe first photoresist pattern and partially removing the secondphotoresist patterns through an ashing process, thereby forming thirdand fourth photoresist patterns; and etching the second metal patternusing the third and fourth photoresist patterns to expose the portion ofthe first metal pattern and form the second source and drain patterns.13. The method of claim 9, wherein the second metal layer has a specificresistance less than the first metal layer, and has a contact resistancefor a conductor greater than the first metal layer.
 14. The method ofclaim 9, wherein the first metal layer is made of one of Al, Al alloy,Cu, Ni, Cr, Ti, Pt, Ta, Ti alloy, Mo and Mo alloy, and the second metallayer is made of one of Cu, Au and Mo.
 15. The method of claim 9,wherein oxidizing the exposed portion of the first metal pattern to forman oxide layer is conducted using an oxygen plasma treatment or athermal treatment under oxygen atmosphere for the exposed portion of thefirst metal pattern.
 16. The method of claim 9, wherein thesemiconductor layer includes a channel region and source and drainregions at both sides.
 17. The method of claim 16, further comprisingforming a first insulating layer on the channel region.
 18. The methodof claim 17, wherein the gate electrode is on the first insulatinglayer.
 19. The method of claim 9, further comprising: forming a secondinsulating layer on the source and drain electrodes; forming a contacthole in the second insulating layer, the contact hole exposing the drainelectrode; and forming a pixel electrode that is on the secondinsulating layer and contacts the drain electrode through the contacthole.